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specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use. d0810 sy 20101028-s00006 no.a1894-1/40 LV766106C overview the LV766106C is vif/sif/y/c/d/deflection /cbcr in implemented in a single chip for pal/ntsc color television sets.(*1) functions ? vif / sif / y / c / deflection / cbcr in / implemented in a single chip with cpu ? i 2 c bus control specifications bip chip maximum ratings at ta=25 c parameter symbol conditions ratings unit allowable power dissipation pd max ta 65 c (*2) 1.3 w operating temperature topr -10 to +65 c storage temperature tstg -55 to +150 c v62 max 6.0 v maximum supply voltage v4 max 6.0 v i9 max 15 ma i20 max 20 ma maximum supply current i49 max 40 ma (*1) -controller chip lc873664a , c maskrom=64kbyte(program_rom:48kbyte character_rom:16kbyte) (this production is produced and sold by sanyo unde r license of the silicon storage technology inc.) (*2) provided with a glass epoxy board (2301501.6 mm) monolithic linear ic for pal/ntsc color television sets vif/sif/y/c/deflection /cbcr in implemented in a single chip orderin g numbe r : ena1894 free datasheet http:///
LV766106C no.a1894-2/40 bip operating conditions at ta=25 c parameter symbol conditions ratings unit v 62 5.0 v recommended supply voltage v 4 5.0 v i 9 10 ma i 20 13 ma recommended supply current i 49 30 ma v 62 4.7 to 5.3 v operating supply voltage range v 4 4.7 to 5.3 v i 9 7 to 13 ma i 20 11 to 15 ma operating supply current range i 49 28 to 35 ma package dimensions unit : mm (typ) 3300 sanyo : dip64s(600mil) 57.2 0.5 0.95 (1.01) 1.78 (4.25) 3.8 5.1max 0.51min 13.8 15.24 0.2 1 32 64 33 free datasheet http:///
LV766106C no.a1894-3/40 -controller chip absolute maximum ratings at ta=25 c, v ss =0v limits parameter symbol pins conditions v dd [v] min typ max unit maximum supply voltage v dd max cpuv dd -0.3 ~ +6.0 input voltage v i xt1,res# -0.3 ~ v dd +0.3 v o 1 xt2,filt -0.3 ~ v dd +0.3 output voltage v o 2 cpuvdd2 -0.3 ~ 3.3v+0.3 input/output voltage v io ports0,1 -0.3 ~ v dd +0.3 v peak output current i o ph ports04~07,1 ? cmos output ? for each pin. -10 mean output current i o mh ports04~07,1 ? cmos output ? for each pin. -1 high level output current total output current i o ah ports04~07,1 the total of all pins. -25 peak output current i o pl ports0,1 for each pin 20 i o ml1 p02,p03,p06,p07 ports1 for each pin 1 mean output current i o ml2 p00,p01,p04,p05 for each pin 8 i o al1 p02,p03,p06,p07 ports1 the total of all pins. 45 low level output current total output current i o al2 p00,p01,p04,p05 the total of all pins. 16 ma -conttoller chip recommended operating range at ta=-10 c to +65 c, v ss =0v limits parameter symbol pins conditions v dd [v] min. typ. max. unit operating supply voltage range v dd cpuv dd 0.229s tcyc 200s 4.5 5.5 hold voltage v hd cpuv dd rams and the registers data are kept in hold mode. 2.0 5.5 v i h1 ports0,1, p00 port input /interrupt 4.5 to 5.5 0.3v dd +0.7 v dd v i h2 port00 watch-dog timer 4.5 to 5.5 0.9v dd v dd high level input vo l t a g e v i h3 res# 4.5 to 5.5 0.75v dd v dd v i l1 ports0,1, p00 port input /interrupt 4.5 to 5.5 v ss 0.1v dd +0.4 v i l2 port00 watch-dog timer 4.5 to 5.5 v ss 0.8v dd -1.0 low level input vo l t a g e v i l3 res# 4.5 to 5.5 v ss 0.25v dd v t cyc 1 all functions operating 4.5 to 5.5 0.231 operation cycle time (*3) t cyc 2 osd and data slicer are not operating 4.5 to 5.5 0.231 200 s fmv co 1 built-in vco1 oscillation sy stem clock 4.5 to 5.5 13.0 ocksel=0 12.5 fmv co 2 (*4) built-in vco2 oscillation osd clock ocksel=1 4.5 to 5.5 16.6 fmrc built-in rc oscillation 4.5 to 5.5 0.3 1.0 2.0 mhz oscillation frequency range fsx?tal (*4) xt1(p07), xt2(p06) at the 32.768khz crystal oscillating s ee the figure1 4.5 to 5.5 32.768 khz oscillation stabilizing time tmsv co ? after the hold mode ? power-on 4.5 to 5.5 300 ms (*3) relational expression between tcyc and oscillation frequency; 1/1 frequency dividing: 3/fmvco1, 1/2 fre quency dividing: 6/fv co 1. (*4) ocksel is the selectable register for osd cloc k frequency. (see the lc873600 users manual for details.) (*5)when the base timer count of clock accu racy is necessary , use the port terminal (two ports) as the crystal oscillation. (see the [11 -controller chip crystal oscillation circui t and sample characteristics] for details.) free datasheet http:///
LV766106C no.a1894-4/40 bip chip electrical characteristics at ta=25 c, i cc =i 9 =10ma i cc =i 20 =13ma i cc =i 49 =30ma v cc =v 62 = v 4 =5.0v parameter symbol conditions min typ max unit [circuit voltage, current] horizontal supply voltage v 20 i 20 =13ma 4.7 5.0 5.3 v logic supply voltage v 9 i 9 =10ma 3.0 3.3 3.6 v rgb supply voltage v 49 i 49 =30ma 7.8 8.15 8.5 v if supply current i 62 v 62 =5.0v 56 65 74 ma video supply current i 4 v 4 =5.0v 65 77 89 ma [vif block] maximum rfagc voltage vrfh cw=80 db, dac=0 4.3 4.7 5 vdc minimum rfagc voltage vrfl cw=80 db, dac=63 0 0.3 0.7 vdc rf agc delay pt (@dac=0) rfagc0 dac=0 90 ? ? db rf agc delay pt (@dac=63) rfagc63 dac=63 ? ? 80 db input sensitivity vi output-3db ? ? 46 db sync signal tip level v o tip cw=80 db 1.1 1.4 1.7 vdc video output amplitude v o 80dbu,am=78%,fm=15khz 1.90 2.00 2.10 vp_p video s/n s/n cw=80 db 40 45 ? db c-s beat level ic-s v4.43mhz/v1.07mhz 35 ? ? db differential gain dg 80 db, 87.5% video mod ? 5.0 15 % differential phase dp 80 db, 87.5% video mod ? 5.0 10.0 deg apc pull-in range(u) fpu 2.0 ? ? mhz apc pull-in range(l) fpl 1.5 ? ? mhz ntsc trap1(4.5mhz) ntr1 ? ? -27 db bg trap1(5.5mhz) btr1 ? ? -27 db i trap1(6.0mhz) itr1 ? ? -27 db dk trap1(6.5mhz) dtr1 ? ? -27 db [sif block] fm detection output voltage soadj fm=50khz 500 640 780 mvrms fm limiting sensitivity sls output -3db 60 db fm detection output f characteristics sf fm=100khz -1.0 0 5.0 db fm detection output distortion sthd fm=50khz 3.0 % sif s/n ssn d in audio 45.0 db [audio block] volume gain (stereo mode) avgt 1khz -3.0 0.0 +3.0 db frequency characteristic (stereo mode) afreqt ? 20 30 khz total harmonic distortion (stereo mode) athdt d in audio ? 0.2 0.7 % output voltage noise (stereo mode) anot d in audio ? -75 -70 dbv cross talk (stereo mode) actt d in audio ? -80 -70 db volume gain (mono mode) avgm 1khz -3.0 0.0 +3.0 db frequency characteristic (mono mode) afreqm ? 20 30 khz total harmonic distortion (mono mode) athdm d in audio ? 0.2 0.7 % output voltage noise (mono mode) anom d in audio ? -75 -70 dbv mute amute d in audio ? -80 -70 db l/r balance abt 1khz -0.5 0 0.5 db free datasheet http:///
LV766106C no.a1894-5/40 parameter symbol conditions min typ max unit [video block] video overall gain (contrast max) cont127 11.0 13.5 16.0 db contrast adjustment characteristics (normal/max) cont64 -7.0 -4.5 -2.0 db contrast adjustment characteristics (min/max) cont0 -18.0 -15.5 -11.0 db video frequency characteristics 1 ntsc bw1 1.8mhz/100khz , y filter.sys = 00 -6.0 -3.0 0.0 db video frequency characteristics 2 pal bw2 2.2mhz/100khz , y filter.sys = 01 -6.0 -3.0 0.0 db video frequency character istics 3 wide bw3 2.3mhz/100khz , y filter.sys = 10 -6.0 -3.0 0.0 db video frequency characteristics 4 apf bw4 3.4mhz/100khz , y filter.sys = 00,y apf=1 -6.0 -3.0 0.0 db chroma trap amount pal ctrapp y filter.sys = 01 -26.0 -20.0 db chroma trap amount ntsc ctrapn y filter.sys = 00 -26.0 -20.0 db dc restoration rate 1 clampg1 dc.rest=00 95.0 100.0 105.0 % dc restoration rate 2 clampg2 dc.rest=01 102.0 107.0 112.0 % dc restoration rate 3 clampg3 dc.rest=10 105.0 112.0 120.0 % dc restoration rate 4 clampg4 dc.rest=11 118.0 128.0 136.0 % y-dl time1 tdy1 y filter.sys=00 y delay ajust=0100 1.40 ns y-dl time2 tdy2 y filter.sys=01 y delay ajust=0100 1.20 ns y-dl time3 tdy3 y filter.sys=11,delay test=1 y delay ajust=0100 1.60 ns y-dl time4 tdy4 y filter.sys=10 y delay ajust=0100 1.15 ns y-dl time ajust1 tdya1 y filter.sys=00 y delay ajust=0000 1.25 ns y-dl time ajust2 tdya2 y filter.sys=00 y delay ajust=0111 1.45 ns black stretch gain max bkstmax blk.str.gain=10 ,blk.str.start=01 17.0 26.0 42.0 ire black stretch gain mid bkstmid blk.str.gain=01 ,blk.str.start=01 8.0 19.0 33.0 ire black stretch gain min bkstmin blk.str.gain=00 ,blk.str.start=01 1.0 11.0 26.0 ire black stretch start point max (70ire v) bkstthmax blk.str.gain=01 ,blk.str.start=10 -4.0 0.0 6.0 ire black stretch start point mid (50ire v) bkstthmid blk.str.gain=01 ,blk.str.start=01 -5.0 0.0 5.0 ire black stretch start point min (40ire v) bkstthmin blk.str.gain=01 ,blk.str.start=00 -5.0 0.0 5.0 ire sharp32t1 f=2.2mhz,y filter.sys=00, y gamma start=11,c_kill.on=1 1.5 3.0 6.0 db sharp63t1 f=2.2mhz,y filter.sys=00, y gamma start=11,c_kill.on=1 9.0 12.0 15.0 db sharpness variability range ntsc (trap 1 mid) (trap 1 max) (trap 1 min) sharp0t1 f=2.2mhz,y filter.sys=00, y gamma start=11,c_kill.on=1 -14.0 -9.0 -7.5 db sharp32t2 f=2.7mhz,y filter.sys=01, y gamma start=11,c_kill.on=1 1.5 3.0 6.0 db sharp63t2 f=2.7mhz,y filter.sys=01, y gamma start=11,c_kill.on=1 8.5 11.5 15.0 db sharpness variability range pal (trap 2 mid) (trap 2 max) (trap 2 min) sharp0t2 f=2.7mhz,y filter.sys=01, y gamma start=11,c_kill.on=1 -14.0 -11.0 -8.0 db sharp32t4 f=3.0mhz,y filter.sys=10, y gamma start=11,c_kill.on=1 1.5 5.0 8.0 db sharp63t4 f=3.0mhz,y filter.sys=10, y gamma start=11,c_kill.on=1 10.0 13.5 17.0 db sharpness variability range 6mhz trap (trap 4 mid) (trap 4 max) (trap 4 min) sharp0t4 f=3.0mhz,y filter.sys=10, y gamma start=11,c_kill.on=1 -14.0 -11.0 -7.0 db free datasheet http:///
LV766106C no.a1894-6/40 parameter symbol conditions min typ max unit white peak limiter effective point1 wpl1 apl=100% wpl=00 130.0 160.0 190.0 ire white peak limiter effective point2 wpl2 apl=100% wpl=01 90.0 125.0 140.0 ire white peak limiter effective point3 wpl3 apl=100% wpl=10 70.0 105.0 130.0 ire white peak limiter effective point4 wpl4 apl=100% wpl=11 50.0 85.0 120.0 ire y gamma start effective point 1 ygst1 y gamma start=00 y gamma gain=01 55 ire y gamma start effective point 2 ygst2 y gamma start=01 y gamma gain=01 65 ire y gamma start effective point 3 ygst3 y gamma start=10 y gamma gain=01 68 ire y gamma gain 1 ygga1 y gamma start=01 y gamma gain=00 220 ire y gamma gain 2 ygga2 y gamma start=01 y gamma gain=01 250 ire y gamma gain 3 ygga3 y gamma start=01 y gamma gain=10 260 ire gray mode level gray glay mode=1, cross b/w=10 12.5 16.0 19.5 ire horizontal/vertical blanking output level rgbblk 0.0 0.1 0.5 v pre-shoot adjust1 preshoot1 pre-sh oot adj.=00 0.92 0.97 1.02 pre-shoot adjust2 preshoot2 pre-sh oot adj.=11 1.08 1.13 1.18 over-shoot adjust overshoot over-shoot adj.=11 1.08 1.13 1.18 [rgb output(cutoff drive)block] brightness control (normal) brt64 1.8 2.3 2.7 v brightness control (normal-h) brt64h 3.3 3.7 4.1 v hi brightness (max) brt127 40.0 50.0 60.0 ire low brightness (min) brt0 -60.0 -50.0 -40.0 ire cutoff control (min) vbias0 2.3 2.8 3.3 v (bias control) (max) vbias255 3.1 3.6 4.1 v resolution vbiassns - 3.5 - mv/bit sub-bias control resolution vsbiassns 7 mv/bit rgb drive adjustment maximum output rgbout127 1.5 1.7 2.3 vpp rgb output attenuation rgbout0 5 10 13 db [video sw block] video signal input 1dc voltage v in 1dc video sw.=00 1.9 2.2 2.5 v video signal input 1ac voltage v in 1ac video sw.=00 1 vpp video signal input 2dc voltage v in 2dc video sw.=01 1.9 2.2 2.5 v video signal input 2ac voltage v in 2ac video sw.=01 1 vpp video signal input 3dc voltage v in 3dc video sw.=10 1.9 2.2 2.5 v video signal input 3ac voltage v in 3ac video sw.=10 1 vpp video signal input 4dc voltage v in 4dc video sw.=11 1.9 2.2 2.5 v video signal input 4ac voltage v in 4ac video sw.=11 1 vpp svo pin dc voltage svodc video sw.=01,svo sw=1 ycmix=0 1.6 1.9 2.2 v svo pin ac voltage svoac video sw.=01,svo sw=1 ycmix=0 1.7 2 2.3 vpp svo pin ycmix ac voltage svoyc video sw.=01,svo sw=1 ycmix=1 0.1 0.14 0.18 vpp free datasheet http:///
LV766106C no.a1894-7/40 parameter symbol conditions min typ max unit [chroma block]: pal/ntsc common b-y/y amplitude ratio clrby 75 100 150 % color control characteristics 1 clrmn color max/cen 1.6 2.0 2.4 ratio color control characteristics 2 clrmm color max/min 30 40 50 db color control sensitivity clrse 1 2 4 %/bit fsc output level fsc40 a reference value 350 mvpp residual higher harmonic level b e_car_b 300 mvpp residual higher harmonic level r e_car_r 300 mvpp residual higher harmonic level g e_car_g 300 mvpp [chroma block]: pal acc amplitude characteristics 1 accm1_p in put:+6db/0db 0db=40ire 0.7 1.0 1.2 ratio acc amplitude characteristics 2 accm2_p input:-20db/0db 0.7 1.0 1.1 ratio demodulation output ratio r-y/b-y:pal rb_p r-y/b-y_gainbalance, r-y/b-y_angle=center 0.50 0.56 0.67 ratio demodulation output ratio g-y/b-y :pal gb_p r-y/b-y_gainbalance r-y/b-y_angle=center, r-y= no-signal -0.24 -0.19 -0.17 ratio demodulation output ratio g-y/r-y :pal gr_p r-y/b-y_gainbalance r-y/b-y_angle=center, b-y= no-signal -0.56 -0.51 -0.46 ratio demodulation angle r-y/b-y :pal angrb_p r-y/b-y_gainbalance r-y/b-y_angle=center 85 90 95 c killer operating point 0 (pal) killp0 0db=40ire -35 -22 db killer operating point 3 (pal) killp3 0db=40ire -38 -24 db difference between two killer operating points (pal) dkillp killp0-killp3 0.5 6.0 db apc pull-in range (+) pulin+_p 350 hz apc pull-in range (-) pu lin-_p -350 hz [chroma block]:ntsc acc amplitude characteristics 1 accm1_n in put:+6db/0db 0db=40ire 0.7 1.0 1.2 ratio acc amplitude characteristics 2 accm2_n input:-20db/0db 0.7 1.0 1.1 ratio demodulation output ratio r-y/b-y: ntsc rb_n r-y/b-y_gainbalance r-y/b-y_angle =center 0.80 0.90 1.00 ratio demodulation output ratio g-y/b-y: ntsc gb_n r-y/b-y_gainbalance r-y/b-y_angle =center 0.22 0.27 0.38 ratio demodulation angle b-y/r-y : ntsc angbr_n r-y/b-y_gainbalance r-y/b-y_angle =center 95 105 111 c demodulation angle g-y/b-y : ntsc anggb_n r-y/b-y_gainbalance r-y/b-y_angle =center 230 240 250 c killer operating point 0 (ntsc) killn0 0db=40ire -40 -27 db killer operating point 3 (ntsc) killn3 0db=40ire -43 -29 db difference between two killer operating points (ntsc) dkilln killn0-killn3 0.5 6.0 db apc pull-in range (+) pulin+_n 350 hz apc pull-in range (-) pulin-_n -350 hz tint center tincen -10 0 10 deg tint variable range (+) tint+ -35 deg tint variable range (-) tint- 35 deg cr output amplitude cbcr-r cbcr_in=1 ,cross b/w=01 2.5 5.0 vpp cb output ampli tude cbcr-b cbcr_in=1 ,cross b/w=01 3.25 5.75 vpp free datasheet http:///
LV766106C no.a1894-8/40 parameter symbol conditions min typ max unit [ fi lt e r b lo ck ]:chroma bpf characteristic c-bpf1a (3.93mhz) cbpf1a reference: 4.43mhz c.filter.sys=10 -7.5 -3.0 -1.0 db c-bpf1b (4.73/4.13mhz) cbpf1b reference: 4.13mhz c.filter.sys=10 -2.5 1.5 5.5 db c-bpf1c (4.93/3.93mhz) cbpf1c reference: 3.93mhz c.filter.sys=10 -3.5 2.0 7.5 db c-bpf2a (3.93mhz) cbpf2a reference: 4.43mhz c.filter.sys=11 -6.0 -3.0 -1.0 db c-bpf2b (4.73/4.13mhz) cbpf2b reference: 4.13mhz c.filter.sys=11 -4.0 0.0 4.0 db c-bpf2c (4.93/3.93mhz) cbpf2c reference: 3.93mhz c.filter.sys=11 -5.5 0.0 5.5 db apc pull-in range (+) pulin+_n 350 hz apc pull-in range (-) pu lin-_n -350 hz tint center tincen -10 0 10 c tint variable range (+) tint+ -40 c tint variable range (-) tint- 40 c cr output amplitude cbcr-r cbcr_in=1 ,cross b/w=01 1.7 3.4 vpp cb output ampli tude cbcr-b cbcr_in=1 ,cross b/w=01 1.8 3.7 vpp [ fi lt e r b lo ck ]:chroma bpf characteristic c-bpf1a (3.93mhz) cbpf1a reference: 4.43mhz c.filter.sys=10 -6.0 -3.0 -1.0 db c-bpf1b (4.73/4.13mhz) cbpf1b reference: 4.13mhz c.filter.sys=10 -2.5 1.5 5.5 db c-bpf1c (4.93/3.93mhz) cbpf1c reference: 3.93mhz c.filter.sys=10 -3.5 2.0 7.5 db c-bpf2a (3.93mhz) cbpf2a reference: 4.43mhz c.filter.sys=11 -6.0 -3.0 -1.0 db c-bpf2b (4.73/4.13mhz) cbpf2b reference: 4.13mhz c.filter.sys=11 -4.0 0.0 4.0 db c-bpf2c (4.93/3.93mhz) cbpf2c reference: 3.93mhz c.filter.sys=11 -5.5 0.0 5.5 db [deflection block] horizontal free-running frequency fh 15470 15670 15870 hz horizontal pull-in range fh pull 400 hz horizontal output pulse width h duty 36.1 37.6 39.1 s horizontal output pulse saturation voltage v hsat 0 0.2 0.4 v vertical free-running cycle 50 vfr50 312.0 312.5 313.0 h vertical free-running cycle 60 vfr60 262.0 262.5 263.0 h horizontal output pulse phase hphcenpal 3.8 5.8 7.8 s horizontal output pulse phase hphcennt 3.8 5.8 7.8 s horizontal position adjustment range hph range 5bit 1.8 s horizontal position adjustment maximum variability width hph step 180.0 ns horizontal blanking left @0 blkl0 h.blk.l:000 8000 9000 10000 ns horizontal blanking left @7 blkl7 h.blk.l:111 11500 12500 13500 ns horizontal blanking right @0 blkr0 h.blk.r:000 -1600 -600 400 ns horizontal blanking right @7 blkr7 h.blk.r:111 1800 2800 3800 ns horizontal output stop voltage h stop reference 3.30 3.60 3.90 v horizontal phase bow correction @16 hbow16 -0.5 0 0.5 s horizontal phase bow correction @0 hbow0 0.7 1.2 1.7 s horizontal phase bow correction @31 hbow31 -1.5 -1.0 -0.5 s horizontal phase angle correction @16 hang16 -0.5 0 0.5 s horizontal phase angle correction @0 hang0 0.4 0.9 1.4 s horizontal phase angle correction @31 hang31 -1.3 -0.8 -0.3 s free datasheet http:///
LV766106C no.a1894-9/40 parameter symbol conditions min typ max unit vertical ramp output amplitude pal @64 vspal64 v.size:1000000 0.75 1.05 1.35 vp-p vertical ramp output amplitude ntsc @64 vsnt64 v.size:1000000 0.75 1.05 1.35 vp-p vertical ramp output amplitude pal @0 vspal0 v.size:0000000 0.30 0.60 0.9 vp-p vertical ramp output amplitude ntsc @0 vsnt0 v.size:0000000 0.30 0.60 0.9 vp-p vertical ramp output amplitude pal @127 vspal127 v.size:1111111 1.25 1.55 1.85 vp-p vertical ramp output amplitude ntsc @127 vsnt127 v.size:1111111 1.25 1.55 1.85 vp-p vertical ramp dc voltage @32 vdc32 v.dc:10000 2.10 2.40 2.70 vdc vertical ramp dc voltage @0 vdc0 v.dc:00000 1.80 2.10 2.40 vdc vertical ramp dc voltage @63 vdc63 v.dc:11111 2.55 2.85 3.15 vdc vertical position @8 vshift8 v.shift:1000 500 550 600 s vertical position @0 vshift0 v.shift:0000 0 50 100 s vertical position @15 vshift15 v.shift:1111 950 1000 1050 s vertical size correction @0 vpsizecomp v.comp:000 0.89 0.93 0.97 ratio vertical linearity @16 vlin16 v.lin:10000 0.7 1.00 1.30 ratio vertical linearity @0 vlin0 v.lin:00000 1.30 1.60 1.90 ratio vertical linearity @31 vlin31 v.lin:11111 0.35 0.65 0.95 ratio vertical s-shaped correction @16 vscor16 v.sc:10000 0.70 1.00 1.30 ratio vertical s-shaped correction @0 vscor0 v.sc:00000 1.10 1.40 1.70 ratio vertical s-shaped correction @31 vscor31 v.sc:11111 0.30 0.60 0.90 ratio horizontal size correction @0 h size comp h.comp:000 0.18 0.28 0.38 v free datasheet http:///
LV766106C no.a1894-10/40 test conditions at ta=25 c, i cc =i 9 =10ma, i cc =i 20 =13ma, i cc =i 49 =30ma, v cc =v 62 = v 4 =5.0v parameter symbol test point input signal test method bus conditions [circuit voltage,current] horizontal supply voltage (pin 20) v 20 no signal apply a current of 13ma to pin 20 and measure the voltage at pin 20. initial logic supply voltage (pin 9) v 9 no signal apply a current of 11ma to pin 9 and measure the voltage at pin 9. initial rgb supply voltage(pin 49) i 49 no signal apply a current of 12ma to pin 49 and measure the voltag e (v) at pin49. initial if supply current(pin 62) i 62 no signal apply a voltage of 5.0v to pin 62 and measure the incoming dc current (ma). (if agc 2.5v applied) initial video / vertical supply current (pin 4) i 4 no signal apply a voltage of 5.0v to pin 4 and measure the incoming dc current (ma). initial ? vif block input signals and test conditions 1. input signals must be input to the pif in (pin 56) in the test circuit. 2. input signal voltage va lues are the levels at the vif in (pin 56) in the test circuit. 3. signal contents and signal levels 4. bus control condition: vif sys.sw=?000?, apc.sis.test="0",s vo.sw="0",video level=?adj input signal waveform conditions sg1 cw 38.9mhz sg2 cw 34.47mhz sg3 cw 33.4mhz sg4 cw frequency variable sg5 38.9mhz 87.5% video mod. 10-stairstep wave (subcarrier: 4.43mhz) sg6 38.9mhz fm=15khz,am=78% sg7 38.9mhz, 90dbu 87.5% video mod. 50ire luma (carrier: variable) 50ire luma 50ire 9 62 4 49 20 free datasheet http:///
LV766106C no.a1894-11/40 parameter symbol test point input signal test method bus conditions [ vif block ] maximum rf agc voltage vrfh sg1 80db measure the dc voltage at pin 58. rf.agc=?000000? minimum rf agc voltage vrfl sg1 80db measure the dc voltage at pin 58. rf.agc=?111111? rf agc delay pt (@dac=0) rfagc0 sg1 obtain the input level at which the dc voltage at pin 58 becomes 2.5v. rf.agc=?000000? rf agc delay pt (@dac=63) rfagc63 sg1 obtain the input level at which the dc voltage at pin 58 becomes 2.5v. rf.agc=?111111? input sensitivity vi sg6 using an oscilloscope, observe the level at pin 61 and obtain the input level at which the waveform's amplitude becomes 1.4vp-p. sync tip level v o tip sg1 80db measure the dc voltage at pin 61. video output amplitude v o sg6 80db using an oscilloscope, adjust the waveform's amplitude at pin 61 to about 2vpp and measure the waveform?s amplitude. * after this measurement, set "video level dac" to the value adjusted . video s/n s/n sg1 80db measure the noise voltage (vsn) at pin 61 with an rms voltmeter through a 10khz to 5.0mhz band-pass filter and calculate 20log(1.43/vsn). c-s beat level ic-s sg1 sg2 sg3 input a 80db sg1 signal and measure the dc voltage (v60) at pin 60. mix sg1=74db , sg2=64db , and sg3=64db to enter the mixture in the vif in. apply v60 to pin 60 from an external dc p ower supply. using a spectrum analyzer, measure the difference between pin 61?s 4.43mhz component and 1.07mhz component. differential gain dg sg5 80db using a vector scope, measure the level at pin 61. differential phase dp sg5 80db using a vector scope, measure the level at pin 61. apc pull-in range (u),(l) fpu, fpl sg4 80db connect an oscilloscope to pin 61 and adjust the sg4 frequency to a frequency higher than 38.9mhz to bring the pll into unlocked mode. (a beat signal appears.) lower the sg4 frequency and measure the frequency at which the pll locks again. in the same manner, adjust the sg 4 frequency to a lower frequency to bring the pll into unlocked mode. higher the sg4 frequency and measure the frequency at which the pll locks again. nt trap1 (4.5mhz) ntr1 sg7 determine the output level difference between carrier frequencies of 1mhz and 4.5mhz.(reference:1mhz) sif.sys=?00? bg trap 1 (5.5mhz) btr1 sg7 determine the output level difference between carrier frequencies of 1mhz and 5.5mhz.(reference:1mhz) sif.sys=?01? i trap1 (6.0mhz) itr1 sg7 determine the output level difference between carrier frequencies of 1mhz and 6.0mhz.(reference:1mhz) sif.sys=?10? dk trap1 (6.5mhz) dtr1 sg7 determine the output level difference between carrier frequencies of 1mhz and 6.5mhz.(reference:1mhz) sif.sys=?11? 58 58 58 58 61 61 61 61 61 61 61 61 61 61 61 61 free datasheet http:///
LV766106C no.a1894-12/40 ? sif block (fm block) input signals and test conditions unless otherwise specified, the following conditions apply when each measurement is made. 1. bus control condition: if.agc.sw=?1?, sif.sys=?01?,deem-tc=?0?,fm.gain=?0? 2. sw: if1=?on?, pin 19=5v 3. input signals are input to pin 52 and the carrier frequency is 5.5mhz. parameter symbol test point input signal test method bus conditions fm detection output voltage soadj 90db , fm=400hz, fm=50khz measure the 400 hz component (sv1:mvrms) of the fm detection output at pin 64. fm limiting sensitivity sls fm=400hz, fm=50khz measure the input level (db ) at which the 400hz component of the fm detection output at pin 64 becomes -3db relative to sv1. fm detection output characteristics (fm=100khz) sf 90db , fm=100khz fm=50khz set sw: if1="off". measure (sv2: mvrms) the fm detection output of pin 64. calculate as follows: sf=20log(sv1/sv2) [db] fm detection output distortion sthd 90db , fm=400hz, fm=50khz measure the distortion factor of the 400hz component of the fm detection output at pin 64. sif.s/n ssn 90db , cw measure the noise level (din audio, sv4:mvrms) at pin 64. calculate as follows: ssn=20log(sv1/sv4) [db] ? audio block input signals and test conditions unless otherwise specified, the following conditions apply when each measurement is made. 1. bus control condition: audio mute ="0", a.moni.sw="1", fm mute="1", audio sw ="00", vol fil="0", if agc="1"mono mode="0", volume (l/mono) ="0000000" 2. enter an input signal ext1/ext2-lin from pin 2/pin8. 3. enter an input signal ext1/ext2-rin from pin 1/pin7. 4. output signal lout is output to pin 50. 5. output signal rout is output to pin 51. parameter symbol test point input signal test method bus conditions [audio block] vo l u m e g a i n (stereo mode) avgt ext1-lin(2pin) ext2-lin(8pin) =1khz,300mvrms measure the 1khz component (v1:mvrms) at the lout(50pin) and calculate as follows: avgt=20log(v1/300) [db] maximum output voltage (stereo mode) avot ext1-lin(2pin) ext2-lin(8pin) =1khz when the distortion (din.audio) of the lout(pin50) is 1%, measure the voltage level at the ext-lin (pin 2). frequency characteristic (stereo mode) afreqt ext1-lin(2pin) ext2-lin(8pin) =300mvrms measure the voltage level (v2:mv rms) at the lout(pin50) and calculate as follows: aft=20log(v2/300) [db] when the aft is ?3db, measure the frequency at the ext-lin (pin 2). total harmonic distortion (stereo mode) athdt ext1-lin(2pin) ext2-lin(8pin) =1khz,300mvrms measure the distortion (din.audio) of the 1khz component at the lout (50pin). output voltage noise (stereo mode) anot no signal measure the noise level (din audio) at the lout (pin50). cross talk (stereo mode) actt ext1-lin(2pin) ext2-lin(8pin) =1khz,300mvrms measure the 1khz component (v3: mvrms) at the rout (pin51) and calculate as follows: actt=20log(v3/300) [db] vo l u m e g a i n (mono mode) avgm ext1-lin(2pin) ext2-lin(8pin) =1khz,300mvrms measure the 1khz component (v4:mvrms) at the lout (pin50) and calculate as follows: avgm=20log(v4/300) [db] audio sw=10 mono mode=1 maximum output voltage (mono mode) avom ext1-lin(2pin) ext2-lin(8pin) =1khz when the distortion (din.audio) of the lout(pin50) is 1%, measure the voltage level at the ext-lin (pin 2). audio sw=10 mono mode=1 frequency characteristic (mono mode) afreqm ext1-lin(2pin) ext2-lin(8pin) =300mvrms measure the voltage level (v5:mvrms) at the lout (pin50) and calculate as follows: afm=20log(v5/300) [db] when the afm is ?3db, measure the frequency at the ext-lin (pin 2). audio sw=10 mono mode=1 total harmonic distortion (mono mode) athdm ext1-lin(2pin) ext2-lin(8pin) =1khz,300mvrms measure the distortion (din.audio) of the 1khz component at the lout (pin50). audio sw=10 mono mode=1 output voltage noise (mono mode) anom no signal measure the noise level (din audio) at the lout (50pin). mono mode=1 mute amute ext1-lin(2pin) ext2-lin(8pin) =1khz,300mvrms measure the 1khz component (v8:mvrms) at the lout (pin50) and calculate as follows: amute =20log(v8/300) [db] audio.mute =1 l/r balance abt ext1-lin(2pin) ext1-rin(1pin) ext2-lin(8pin) ext2-rin(7pin) =1khz,300mvrms measure the 1khz component(v9:mvrms) at the rout (pin51) and calculate as follows: abt=20log(v1/v9) [db] 64 64 64 64 64 50 50 50 2 2 50 50 51 50 2 2 50 51 free datasheet http:///
LV766106C no.a1894-13/40 ? video block input signals and test conditions 1. ? c in input*chroma burst signal: 40 ire 2. y in input signal 100ire:714mv 3. ? bus control bit conditions : initial test state l 0ire signal (l-0): ntsc standard sync signal pedestal level h sync 4.7 s (h/v sync: 40ire: 286mv) xire signal (l-x) x ire ( x= 0 to 100) 0 ire cw signal (l-cw) 20 ire cw signal 50 ire black stretch a point (0ire to 99ire) signal (l-bk) ? ? r/g/b in input signal rgb input signal 1 (0-1) to each 20 s 0.7v 0.35v 0.0vdc a b rgb input signal 2 (0-2) 20 s 30 s 5.0v 0.0vdc 60 s 100ire 5 s point a ?100ire white signal as other h ? free datasheet http:///
LV766106C no.a1894-14/40 parameter symbol test point input signal test method bus conditions [video block] video overall gain (contrast max) cont127 l-50 measure the output signal?s 50ire amplitude (cnthb vp-p) and calculate cont127= 20log (cnthb/0.357). contrast:1111111 y gamma start=11 contrast adjustment characteristics (normal/max) cont64 l-50 measure the output signal?s 50ire amplitude (cntcb vp-p) and calculate cont63= 20log (cntcb/cnthb). contrast:1000000 y gamma start=11 contrast adjustment characteristics (min/max) cont0 l-50 measure the output signal ?s 50ire amplitude (cntlb vp-p) and calculate cont0=20 log (cntlb/cnthb). contrast:0000000 y gamma start=11 video frequency characteristics 1 (ntsc) bw1 l-cw with the input signal?s continuous wave=100khz, measure the output signal?s continuous wave amplitude (peakdc vpp). with the input signal?s continuous wave=1.8mhz, measure the output signal?s continuous wave amplitude (cw1.8 vpp). calculate bw1=20log (cw1.8/peakdc). y filter.sys:00 sharpness: 001010 y gamma start=11 video frequency characteristics 2 (pal) bw2 l-cw with the input signal?s continuous wave=2.2mhz, measure the output signal?s continuous wave amplitude (cw2.2 vp-p). calculate bw2=20log (cw2.2/peakdc). y filter.sys:01 sharpness: 001010 y gamma start=11 video frequency characteristics 3 (6mhz trap) bw3 l-cw with the in p ut signal?s continuous wave=2.3mhz, measure the output signal?s continuous wave amplitude (cw2.3 vp-p). calculate bw3=20log (cw2.3/peakdc). y filter.sys:10 sharpness: 001010 y gamma start=11 video frequency characteristics 4 (apf) bw4 l-cw with the input signal?s continuous wave=3.4mhz, measure the output signal?s continuous wave amplitude (cw3.4 vp-p). calculate bw3=20log (cw3.4/peakdc). y filter.sys:00 sharpness: 001010 y apf:1 y gamma start=11 chroma trap amount pal ctrapp l-cw with the input signal?s continuous wave=4.43mhz, measure the output signal?s continuous wave amplitude (f0p vp-p). calculate ctrap=20log (f0p/peakdc). y filter.sys:01 sharpness: 000000 y gamma start=11 chroma trap amount ntsc ctrapn l-cw with the input signal?s continuous wave=3.58mhz, measure the output signal?s continuous wave amplitude (f0n vp-p). calculate ctran=20log (f0n/peakdc). y filter.sys:00 sharpness: 000000 y gamma start=11 dc restoration rate 1 clampg1 l-0 measure the output signal?s 0ire dc level (brtpl v). sub.bais:1111111 contrast:0111111 l-100 measure the output signal?s 0ire dc level(drvph v) and 100ire amplitude (dr vh vp-p) and calculate clampg=100 (1+(drvph-brtpl)/drvh). sub.bais:1111111 contrast:0111111 dcrest=00 blk.str.start=11 wpl=0 dc restoration rate 2 clampg2 l-100 with dcrest = 01, carry out measurement similarly to the case of the dc restoration rate 1. dcrest =01 dc restoration rate 3 clampg3 l-100 with dcrest = 10, carry out measurement similarly to the case of the dc restoration rate 1. dcrest =10 dc restoration rate 4 clampg4 l-100 with dcrest = 11, carry out measurement similarly to the case of the dc restoration rate 1. dcrest =11 y- d l t i m e 1 (ntsc) tdy1 l-50 obtain the time difference (the delay time) from when the rise of the input signal's 50ire amplitude to the output signal's 50ire amplitude. y filter.sys:00 ydelay ajust:100 y- d l t i m e 2 (pal) tdy2 l-50 obtain the ti me difference (the delay time) from when the rise of the input signal's 50ire amplitude to the output signal's 50ire amplitude. y filter.sys:01 ydelay ajust:100 y-dl time3 tdy3 l-50 obtain the time diff erence (the delay time) from when the rise of the input signal's 50ire amplitude to the output signal's 50ire amplitude. y filter.sys:11 ydelay ajust:100 delay test:1 y- d l t i m e 4 (6mhz trap) tdy4 l-50 obtain the ti me difference (the delay time) from when the rise of the input signal's 50ire amplitude to the output signal's 50ire amplitude. y filter.sys:10 ydelay ajust:100 y-dl time ajust1 tdya1 l-50 obtain the time difference (the delay time) from when the rise of the input signal's 50ire amplitude to the output signal's 50ire amplitude. y filter.sys:00 y delay ajust:000 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 free datasheet http:///
LV766106C no.a1894-15/40 parameter symbol test point input signal test method bus conditions y-dl time ajust2 tdya2 l-50 obtain th e time difference (the delay time) from when the rise of the input signal's 50ire amplitude to the output signal's 50ire amplitude. y filter.sys:00 y delay ajust:111 measure the 0ire dc level(bkst1 v) at point a of the output signal in the black stretch defeat (black stretch off) mode blk.str.start=11 y filter.sys:10 black stretch gain (max) bkst max l-bk (a=0ire) measure the 0ire dc level(bkst2 v) at point a of the output signal in the black stretch on mode. calculate bkst max=50 (bkst1-bkst2)/cnthb. blk.str.gain=10 blk.str.start=01 y filter.sys:10 black stretch gain (mid) bkst mid l-bk (a=0ire) with blk.str.gain = 01, carry out the same measurement as for the case of black stretch gain (max). blk.str.gain=01 blk.str.start=01 y filter.sys:10 black stretch gain (min) bkst min l-bk (a=0ire) with blk.str.gain = 00, carry out the same measurement as for the case of black stretch gain (max). blk.str.gain=00 blk.str.start=01 y filter.sys:10 measure the 60ire dc level(bkst3 v) at point a of the output signal in the black stretch on mode. blk.str.gain=01 blk.str.start=10 y filter.sys:10 black stretch start max (60ire black) bkstth max l-bk (a=60ire) measure the 60ire dc level(bkst4 v) at point a of the output signal in the black stretch defeat (black stretch off) mode. calculate bkstthmax=50(bkst4-bkst3)/cnthb. blk.str.gain=00 blk.str.start=11 y filter.sys:10 measure the 50ire dc level(bkst 5 v) at point a of the output signal in the black stretch defeat on mode. blk.str.gain=01 blk.str.start=01 y filter.sys:10 black stretch start mid (50ire black) bkstth mid l-bk (a=50ire) calculate bkstthmid=50 bkst6-bkst5)/cnthb. blk.str.gain=00 blk.str.start=11 y filter.sys:10 measure the 40ire dc level(bkst7 v) at point a of the output signal in the black stretch defeat on mode. blk.str.gain=01 blk.str.start=00 y filter.sys:10 black stretch start min (40ire black) bkstth min l-bk (a=40ire) measure the 40ire dc level(bkst8 v) at point a of the output signal in the black stretch defeat (black stretch off) mode. calculate bkstthmin=50(bkst8-bkst7)/cnthb. blk.str.gain=00 blk.str.start=11 y filter.sys:10 sharpness variable range (ntsc) sharp32t1 l-cw with the input signal?s continuous wave=2.2mhz, measure the output signal?s continuous wave amplitude (f01s32 vp-p). calculate sharp32t1=20log (f01s32/peakdc). y filter.sys:00 sharpness: 100000 y gamma start=11 c_kill.on=1 (max) sharp63t1 l-cw with the input signal?s continuous wave=2.2mhz, measure the output signal?s continuous wave amplitude (f01s63 vpp). calculate sharp63t1=20log (f01s63/peakdc). y filter.sys:00 sharpness: 111111 y gamma start=11 c_kill.on=1 (min) sharp0t1 l-cw with the input signal?s continuous wave=2.2mhz, measure the output signal?s continuous wave amplitude (f01s0 vpp). calculate sharp0t1=20log (f01s0/peakdc). y filter.sys:00 sharpness: 000000 y gamma start=11 c_kill.on=1 sharpness variable range (pal) sharp32t2 l-cw with the input signal?s continuous wave=2.7mhz, measure the output signal?s continuous wave amplitude (f02s32 vpp). calculate sharp32t3= 20log (f02s32/ peakdc). y filter.sys:01 sharpness: 100000 y gamma start=11 c_kill.on=1 (max) sharp63t2 l-cw with the input signal?s continuous wave=2.7mhz, measure the output signal?s continuous wave amplitude (f02s63 vpp). calculate harp63t2= 20log (f02s63/ peakdc). y filter.sys:01 sharpness: 111111 y gamma start=11 c_kill.on=1 (min) sharp0t2 l-cw with the input signal?s continuous wave=2.7mhz, measure the output signal?s continuous wave amplitude (f02s0 vpp). calculate sharp0t2=20log (f02s0/peakdc). y filter.sys:01 sharpness: 000000 y gamma start=11 c_kill.on=1 46 46 46 46 46 46 46 46 46 46 46 46 46 free datasheet http:///
LV766106C no.a1894-16/40 parameter symbol test point input signal test method bus conditions sharpness variable range (6mhz trap) sharp32t4 l-cw with the input signal?s continuous wave=3.0mhz, measure the output signal?s continuous wave amplitude (f04s32 vpp). calculate shar p32t4=20log (f04s 32/peakdc). y filter.sys:10 sharpness: 100000 y gamma start=11 c_kill.on=1 (max) sharp63t4 with the input signal?s continuous wave=3.0mhz, measure the output signal?s continuous wave amplitude (f04s63 vpp). l-cw calculate sharp63t4= 20log (f04s63/ peakdc). y filter.sys:10 sharpness: 111111 y gamma start=11 c_kill.on=1 (min) sharp0t4 with the input signal?s continuous wave=3.0mhz, measure the output signal?s continuous wave amplitude (f04s0 vpp). l-cw calculate sharp0t4=20log (f04s0/peakdc). y filter.sys:10 sharpness: 000000 y gamma start=11 c_kill.on=1 white peak limiter operating point 1 wpl1 l-100 measure the ampritude(from pedestal to white) of the output signal with wpl=00. (pin 45: 5v) bigger the input signal and measure the amplitude (from pedestal to white) of the output signal at which the output signal is clipped. (wp1) wpl1=wp1/cntcb1*100 wpl=00 y gamma start=11 white peak limiter operating point 2 wpl2 l-100 bigger the input signal and measure the amplitude(from pedestal to white) of the output signal at which the output signal is clipped with wpl=01. (wp2) wpl2=wp2/cntcb1*100 wpl=01 y gamma start=11 white peak limiter operating point 3 wpl3 l-100 bigger the input signal and measure the amplitude(from pedestal to white) of the output signal at which the output signal is clipped with wpl=10. (wp3) wpl3=wp3/cntcb1*100 wpl=10 y gamma start=11 white peak limiter operating point 4 wpl4 l-100 bigger the input signal and measure the amplitude(from pedestal to white) of the output signal at which the output signal is clipped with wpl=11. (wp4) wpl4=wp4/cntcb1*100 wpl=11 y gamma start=11 l-100 measure the amplitude of the output signal (0 to 100ire) with y gamma start=3.y gamma gain=0. (gam0) y gamma gain=00 y gamma start=11 y gamma start effective point1 ygst1 l-50 next measure the amplitude the o utput signal (0 to 50ire) with y gamma start=1. y gamma gain=1(gam1) and calculate ygs1= gam1/gam0*100 y gamma gain=01 y gamma start=00 y gamma start effective point12 ygst2 l-50 measure the amplitude of the output signal (0 to 50ire) with y gamma start=1. y gamma gain=1 (gam2) and calculate ygs2= gam2/gam0*100 y gamma gain=01 y gamma start=01 y gamma start effective point1 ygst3 l-50 measure the amplitude of the output signal (0 to 50ire) (gam3) and calculate ygs3= gam3/gam0*100 y gamma gain=01 y gamma start=10 l-50 measure the amplitude of the output signal (0 to 50ire).(ggam1) y gamma gain 1 ygga1 l-100 measure the amplitude of the output signal (0 to 100ire).(ggam2) calculate ygg1=100*ggam1/(ggam2-ggam1) y gamma start =01 y gamma gain=00 l-50 measure the amplitude of the output signal (0 to 50ire).(ggam3) y gamma gain 2 ygga2 l-100 measure the amplitude of the output signal (0 to 100ire).(ggam4) calculate ygg2=100*ggam3/(ggam4-ggam3) y gamma start =01 y gamma gain=01 l-50 measure the amplitude of the output signal (0 to 50ire) .(ggam5) y gamma gain 3 ygga3 l-100 measure the amplitude of the output signal (0 to 100ire).(ggam6) calculate ygg3=100*ggam5/(ggam6-ggam5) y gamma start =01 y gamma gain=10 gray mode level gray measure the dc level(deviation from pedestal)of pin46, and transfer ire. cross b/w:10 gray mode:1 horizontal/vertical blanking output level rgbblk l-100 measure the dc level (rgbblk v) for the output signal?s blanking period. pre-shoot adjust1 preshoot1 l-100 measure the pre-shoot width (tpre) and over-shoot width (tover) at rise of 100ire amplitude of the output signal, and calculate preshoot = tpre / tover. pre-shoot adj.=00 y filter.sys:00 sharpness=111111 pre-shoot adjust2 preshoot2 l-100 with pre-shoot adj. = 11, carry out the same measurement as for the case of pre-shoot 1. pre-shoot adj.=11 y filter.sys:00 sharpness=111111 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 free datasheet http:///
LV766106C no.a1894-17/40 parameter symbol test point input signal test method bus conditions over-shoot adjust overshoot l-100 with over-shoot adj. = 11measure the pre-shoot width (tpre) and over-shoot width (tover) at rise of 100ire amplitude of the output signal, and calculate overshoot = tover/tpre over-shoot adj.=11 y filter.sys:00 sharpness=111111 [rgb output block] (cutoff, drive block) bus control bit conditions: contrast=127 contrast:1111111 brightness control (normal) brt64 l-0 measure the 0ire dc levels of the respective output signals of r output (48), g output (47), and b output (46). assign the measured values to brtpcr, brtpcg, and brtpcb v, respectively. calculate brt63=(brtpcr+brtpcg+brtpcb)/3 bright: 1000000 brightness control (normal-h) brt64h l-0 measure the 0ire dc level of the output signal of b output (46) and assign the measured value to brtpcbh. bright: 1000000 b.bias: 11111111 sub bias: 1111111 brightness control (max) brt127 l-0 measure the 0ire dc level of the output signal of b output (46) and assign the measur ed value to brtphb. calculate brt127=50 (brtphbh-brtpcb)/cnthb. bright: 1111111 b.bias: 11111111 sub bias: 1111111 brightness control (min) brt0 l-0 measure the 0ire dc level of the output signal of b output (46) and assign the measur ed value to brtplb. calculate brt0=50(brt plb-brtpcbh)/cnthb. bright: 0000000 b.bias: 11111111 sub bias: 1111111 bias (cutoff) control (min) vbias0 l-50 measure the 0ire dc levels (vbias0 v)of the respective output signals of r output (48), g output (47), and b output (46). ( : r, g, and b) sub.bias: 1111111 bias (cutoff) control (max) vbias255 l-50 measure the 0ire dc levels (vbias255 v)of the respective output signals of r output (48), g output (47), and b output (46). ( : r, g, and b) sub.bias: 1111111 r/g/b.bias:11111111 bias (cutoff) control resolution vbiassns l-50 measure the 0ire dc levels (bas80 v) of the respective output signals of r output (48), g output (47), and b output (46). ( : r, g, and b) measure the 0ire dc levels (bas48 v)of the respective output signals of r output (48), g output (47), and b output (46). calculate vbiassns = (bas80 -bas48 )/32 r/g/b.bias:01010000 sub.bias: 1111111 r/g/b.bias:00110000 sub.bias: 1111111 sub-bias control resolution vsbiassns l-50 set sub.bias 64 and measure the 0ire dc levels (sb64 v) of the respective output signals of r output (48),g output(47), and b output(46).and next,set sub.bias 42,then measure the same as before. calculate vsbiassns -(sb64 -sb42 )/22 sub.bias: 1000000/0101010 contrast: 0111111 r/g/b.bias:11111111 drive adjustment maximum output rgbout127 l-100 measure the 100ire amplitudes (drvh vp-p)of the respec tive output signals of r output (48),g output(47) and b output (46). ( : r, g and b) bright: 0000000 r/g/b drive: 1111111 contrast: 1000000 output attenuation rgbout0 l-100 measure the 100ire amplitudes (drvl vp-p) of the respective output signals of r output (48), g output (47), and b output (46). ( : r, g and b) calculate rgbout0 =20log(drvh /drvl ) bright: 0000000 r/g/b drive: 0000000 contrast: 1000000 48 47 46 48 47 46 48 47 46 48 47 46 46 46 48 47 46 48 47 46 48 47 46 46 46 free datasheet http:///
LV766106C no.a1894-18/40 parameter symbol test point input signal test method bus conditions [video sw [block] video signal input 1dc voltage vin1dc l-100 input signals to pin 5 and measure the voltage of the pedestal. video sw:01 video signal input 1 ac voltage vin1ac pin 5 recommended input level video sw:01 video signal input 2dc voltage vin2dc l-100 input signals to pin 3 and measure the voltage of the pedestal. video sw:00 video signal input 2 ac voltage vin2ac pin 3 recommended input level video sw:00 video signal input 3dc voltage vin3dc input signals to pin 10 and measure the voltage of the pedestal. video sw:10 video signal input 3ac voltage vin3ac pin 10 recommended input level video sw:10 video signal input 4dc voltage vin4dc input signals to pin 7 and measure the voltage of the pedestal. video sw:11 video signal input 4ac voltage vin4ac pin 7 recommended input level video sw:11 svo terminal dc voltage svodc l-100 input signals to pin 5 and measure the voltage of the pedestal at pin 61. video sw:01 svo sw:1 ycmix:0 svo terminal ac voltage svoac l-100 the signal is input to 5pin, and the amplitude of the signal of 61pin is measured. vide0 sw:01 svo sw:1 ycmix:0 svo terminal ycmix ac voltage svoyc l-0 l-cw y signal is input to 7pin, and c signal of 8pin is input, and the amplitude of 61pin (svo) is measured. vide0 sw:11 svo sw:1 ycmix:1 5 5 3 3 10 10 7 7 61 61 61 free datasheet http:///
LV766106C no.a1894-19/40 ? chroma block input signals and test conditions unless otherwise specified, the following conditions apply when each measurement is made. 1. vif, sif blocks: no signal 2. deflection block: horiz ontal/vertical composite sync signal s are input and the deflection block must be locked into the sync signals (refer to the deflection block input signals and the test conditions). 3. bus control conditions: set the followi ng conditions unless otherwise specified. y input is 7 pin (yc-y), c input is 8 pin (yc-c) (video sw=3, c. ext=1) other dac except the above-mentioned conditions is all initial conditions. 4. y input condition: no signal unless otherwise specified. (sync is necessary to obtain synchronization). 5. how to calculate the de modulation ratio and angle: b-y axis angle=tan-1(b ( 0) / b (270))+270 r-y axis angle=tan-1(r (180) / r ( 90))+90 g-y axis angle=tan-1(g (270) / g (180))+180 b-y axis amplitude vb=sqrt(b(0)*b(0)+b(270)*b(270)) r-y axis amplitude vr=sqrt(r(180)*r(180)+r(90)*r(90)) g-y axis amplitude vg=sqr t(g(180)*g(180)+g(270)*g(270)) 90 180 270 0 b(0) r(90) g(270) r(180) g(180) b(270) r-y axis b-y axis g-y axis free datasheet http:///
LV766106C no.a1894-20/40 6. chroma input signal as for the pal signal, the burst swings such as 135 and 225 every horizontal period. chroma describes the phase caused when the burst occurs at 135. as for the ntsc signal, the burst occurs constantly at 180. the figures below are based on the phase of ntsc. when a pal signal is generated, adjust the phase and then enter signals. the item common to both pal and ntsc is the pal signal. for those other than this, the measurement must be performed for each individual signals. the condition of fsc: set the followi ng conditions unless otherwise specified. pal =4.433619mhz ntsc =3.579545mhz c-1 x ire signal (l-x) c-2 c-3 c-4 c-5 c-6 burst 0 o 90 o 180 o 270 o fsc 40ire burst fsc 346 deg 40ire 40ire burst fsc cw (note: fsc n*fh when the freque ncy is specified. should be a natural number and the nearest value should be used.) 40ire burst b-y only burst r-y only 0.35v 0.35v *there is no signal for h, v blanking period. free datasheet http:///
LV766106C no.a1894-21/40 parameter symbol test point input signal test method bus conditions [chroma block]: pal/ntsc common clrby yin:l 77 cin: no signal measure the y system?s output level. v 1 b-y/y amplitude ratio c-2 input a signal to the c in (only sync signal to the yin) and measure the output level to calculate as follows: clrby=100 (v2/v1) color:1000000 color control characteristics 1 clrmn c-1 measure the output amplitude v 1 at color control max mode and output amplitude v2 at color control cen mode and, calculate as follows: clrmn=v 1 /v 2 color:1111111 color:1000000 color control characteristics 2 clrmm c-1 measure the output amplitude v 3 at color control min mode to calculate as follows: clrmm=20log (v 1 /v 3 ) color:0000000 color control sensitivity clrse c-1 measure the output amplitude v4 at color control 90 mode and output amplitude v5 at color control 38 mode to calculate as follows: clrse=100 (v 4 ? v 5 )/(v 2 52) color:1011010 color:0100110 residual higher harmonic level b e_car_b c-1 burst only measure the 8.86mhz component output amplitude at pin 46. residual higher harmonic level g e_car_g c-1 burst only measure the 8.86mhz component output amplitude at pin 47. residual higher harmonic level r e_car_r burst only measure the 8.86mhz component output amplitude at pin 48. [chroma block]: pal acc amplitude characteristics 1 accm1_p c-1 0db +6db measure the output amplitude when 0db is applied to the chroma inputand when +6db is applied to the chroma input. and calculate the ratio between them. accm1_p=20log(+6dbdata/0dbdata) color:1000000 acc amplitude characteristics 2 accm2_p c-1 -20db measure the output amplitude when ?20db is applied to the chroma input and calculate the ratio between them. accm2_p=20log(-20dbdata/0dbdata) color:1000000 demodulation output ratio r-y/b-y:pal rb_p c-1 refer to 5. and measure bout output amplitude vb and r out output amplitude vr. and calculate rb_p=vr/vb. color:1000000 demodulation output ratio g-y/b-y:pal gb_p c-4 measure bout output amplitude vbp and g out output amplitude vgbp. and calculate gb_p=vgbp/vbp. color:1000000 demodulation output ratio g-y/r-y:pal gr_p c-5 measure r out output amplitude vrp and g out output amplitude vgbp. and calculate gr_p=vgrp/vrp. color:1000000 demodulation angle r-y/b-y:pal angrb_p c-1 refer to 5. and measure the b-y and r-y demodulation angle and calculate. color:1000000 killer operating point 0 (pal) killp0 c-1 reduce the input signal until the output level becomes 75mvp- p or less. measure the input level at that moment. color killer ope.:00 killer operating point 3 (pal) killp3 c-1 reduce the input signal until the output level becomes 75mvp- p or less. measure the input level at that moment. color killer ope.:11 difference between two killer operat ing points (pal) dkillp calculate as follows, dkillp=killp0-killp3 apc pull-in range(+) pulin+_p c-1 decrease the chroma fsc frequen cy from 4.433619mhz+1000hz and measure the frequency at which the v co locks. apc pull-in range(-) pulin-_p c-1 increase the chroma fsc frequen cy from 4.433619mhz-1000hz and measure the frequency at which the v co locks. 46 46 46 46 46 47 48 46 46 46 48 46 47 47 48 46 48 46 46 46 46 free datasheet http:///
LV766106C no.a1894-22/40 parameter symbol test point input signal test method bus conditions [chroma block]: ntsc acc amplitude characteristics 1 accm1_n c-1 0db +6db measure the output amplitude when 0db is applied to the chroma input and when +6db is applied to the chroma input. and calculate the ra tio between them. accm1_n=20log(+6dbdata/0dbdata) acc amplitude characteristics 2 accm2_n c-1 -20db measure the output amplitude when 20db is applied to the chroma input and calculate the ra tio between them. accm2_n=20log(-20 dbdata/0dbdata) demodulation output ratio r-y/b-y:ntsc rb_n c-1 refer to 5. and measure bout output amplitude vb and rout output amplitude vr. and calculate rb_n=vr/vb. color:1000000 demodulation output ratio g-y/b-y:ntsc gb_n c-1 refer to 5. and measure g out output amplitude vg. and calculate gb_n=vg/vb. color:1000000 demodulation angle b-y/r-y: ntsc angbr_n c-1 refer to 5. and measure the b-y and r-y demodulation angle and calculate. reference: b-y angle color:1000000 demodulation angle g-y/b-y: ntsc anggb_n c-1 refer to 5. and measure the b-y and g-y demodulation angle and calculate. reference: b-y angle color:1000000 killer operating point 0 (ntsc) killn0 c-1 reduce the input signal until the output level becomes 75mvp-p or less. measure the input level at that moment. color killer ope.:00 killer operating point 3 (ntsc) killn3 c-1 reduce the input signal until the output level becomes 75mvp-p or less. measure the input level at that moment. color killer ope.:11 difference between two killer operating points (ntsc) dkilln calculate as follows, dkilln=killn0-killn3 apc pull-in range(+) pulin+_n c-1 decrease the chroma fsc frequency from 3.579545mhz+1000hz and measure the frequency at which the v co locks. apc pull-in range(-) pulin-_n c- 1 increase the chroma fsc frequen cy from 3.579545 mhz-1000hz and measure the frequency at which the v co locks. tint center tincen c-1 measure each part of the output level and calculate the b-y axis angle. tint:1000000 tint variable range (+) tint+ c-1 measure each pa rt of the output level and calculate the b-y axis angle. tint+ =b-y axis angle ?tincen tint:1111111 tint variable range (-) tint- c-1 measure each pa rt of the output level and calculate the b-y axis angle. tint- =b-y axis angle ?tincen tint:0000000 cr output am plitude cbcr-r r-y in:c-6 measure the output amplitude. (b-y in:no signal) cbcr in: 1 color sys:101 cross b/w: 01 cb output amplitude cbcr-b b-y in:c-6 measure the output amplitude. (r-y in:no signal) cbcr in: 1 color sys: 101 cross b/w: 01 [filter block]:chroma bpf characteristic c-bpf1a peaker amplitude characteristic 3.93mhz cbpf1a c-3 pal signal set the chroma frequency (cw) to 4.433619mhz-100khz and measure v 0 output amplitude. and then, set the chroma frequency (cw) to 3.93mhz and measure v 1 output amplitude to calculate as follows: cbpf1a=20log(v 1 /v 0 ) c.filter.sys:10 c.bypass:0 c-bpf1b peaker amplitude characteristic 4.73/4.13mhz cbpf1b c-3 pal signal measure v 2 output amplitude when the chroma frequency (cw) is 4.13mhz and v 3 output amplitude when it (cw) is 4.73mhz to calculate as follows: cbpf1b =20log(v 3 /v 2 ) c.filter.sys:10 c.bypass:0 c-bpf1c peaker amplitude characteristic 4.93/3.93mhz cbpf1c c-3 pal signal set the chroma frequency (cw) to 4.93mhz and measure v 4 output amplitude to calculate as follows: cbpf1c =20log(v 4 /v 1 ) c.filter.sys:10 c.bypass:0 c-bpf2a bandpass amplitude characteristic 3.93mhz cbpf2a c-3 pal signal set the chroma frequency (cw) to 4.433619mhz-100mhz and measure v 00 output amplitude. and then, set the chroma frequency (cw) to 3.93mhz and measure v 10 output amplitude to calculate as follows: cbpf2a=20log(v 10 /v 00 ) c.filter.sys:11 c.bypass:0 c-bpf2b bandpass amplitude characteristic 4.73/4.13mhz cbpf2b c-3 pal signal measure v 20 output amplitude when the chroma frequency (cw) is 4.13mhz and v 30 output amplitude when it (cw) is 4.73mhz to calculate as follows: cbpf2b =20log(v 30 /v 20 ) c.filter.sys:11 c.bypass:0 c-bpf2c bandpass amplitude characteristic 4.93/3.93mhz cbpf2c c-3 pal signal set the chroma frequency (cw) to 4.93mhz and measure v 40 output amplitude to calculate as follows: cbpf2c =20log(v 40 /v 10 ) c.filter.sys:11 c.bypass:0 46 46 46 46 46 46 46 48 47 48 47 46 46 46 46 46 46 46 46 46 46 46 46 48 free datasheet http:///
LV766106C no.a1894-23/40 ? deflection block input signals and test conditions unless otherwise specified the following conditions apply when each measurement is made. 1. vif, sif blocks: no signal 2. c input: no. signal 3. sync input: a horizontal/ver tical composite sync signal pal: 43ire, horizontal sync signal (15.625khz) and vertical sync signal (50khz) ntsc: 40ire, horizontal sync signal (15.734264khz) and vertical sync signal (59.94khz) note: no burst signal, chroma signal shall exist below the pedestal level. 4. bus control conditions: initial c onditions unless otherwise specified 5. the delay time from the rise of the horizontal output (pin 22 output) to the fall of the fbp in (pin 23 input) is 7 s. 6. pin 15 (vertical size correction circ uit input terminal) is connected to v cc (5.0v). parameter symbol test point input signal test method bus conditions [deflection block] horizontal free-running frequency fh yin: no signal connect a frequency counter to the output of pin 22 (h out) and measure the horizontal free-running frequency. horizontal pull-in range fh pull yin: horizontal /vertical sync signal pal using an oscilloscope, monitor the horizontal sync signal which is input to the y in (pin 5) and the pin 22 output (h out) and vary the horizontal signal frequency to measure the pull-in range. horizontal output pulse length hduty yin: horizontal /vertical sync signal pal measure the voltage for the pin 22 horizontal output pulse?s low-level period. horizontal output pulse saturation voltage v hsat yin: horizontal /vertical sync signal pal measure the voltage for the pin 22 horizontal output pulse?s low-level period. vertical free-running period 50(pal) vertical free-running period 60(ntsc) vfr50 vfr60 yin: no signal measure the vertical output period t at pin 17. t 15.625khz (pal) t 15.734khz (ntsc) cdmode:001 (pal) cdmode:010 (ntsc) horizontal output pulse (pal)(ntsc) hphcen (pal) (ntsc) y in: horizontal /vertical sync signal pal ntsc measure the delay time from to the rise of the pin 22 horizontal output pulse to the fall of the y in horizontal sync signal. burst signal chroma signal signal unsuitable for y input signal suitable for y input t 2.5v vertical ramp output 22 22 22 22 5 17 22 5 2.5v 20ire horizontal output measuring hphcen free datasheet http:///
LV766106C no.a1894-24/40 parameter symbol test point input signal test method bus conditions horizontal position adjustment range hphrange y in: horizontal /vertical sync signal pal with h.phase: 0 and 31, measure the delay time from the rise of the pin 22 horizontal output pulse to the fall of the y in horizontal sync signal and calculate the difference from h phcen. h.phase:00000 to h.phase:11111 horizontal position adjustment maximum variable width hphstep y in: horizontal /vertical sync signal pal with h.phase: 0 to 31 varied, measure the delay time from to the rise of the pin 22 horizontal output pulse to the fall of the y in horizontal sync signal and calculate the variation at each step. retrieve data for maximum variation. horizontal output h.phase:00000 to h.phase:11111 horizontal position adjustment maximum variable width hphstep y in: horizontal /vertical sync signal pal with h.phase: 0 to 31 varied, measure the delay time from to the rise of the pin 22 horizontal output pulse to the fall of the y in horizontal sync signal and calculate the variation at each step. retrieve data for maximum variation. horizontal output h.phase:00000 to h.phase:11111 horizontal blanking left variable range@0 blkl0 y in: horizontal /vertical sync signal pal measure the time t from the left end of hsync at pin 5 y in to the right end of blanking period at pin 46 blueout with h.blk.l = 000. h.blk.l:000 horizontal blanking left variable range@7 blkl7 y in: horizontal /vertical sync signal pal measure the time t from the left end of hsync at pin 5 y in to the right end of blanking period at pin 46 blueout with h.blk.l = 111. h.blk.l:111 20ire measuring hphcen 2.5v 20ire measuring hph cen 22 5 22 5 2.5v 20ire horizontal output measuring hphcen 22 5 blue hsync y in t 46 5 46 5 blue hsync y in t free datasheet http:///
LV766106C no.a1894-25/40 parameter symbol test point input signal test method bus conditions horizontal blanking right variable range@0 blkr0 y in: horizontal /vertical sync signal pal measure the time t from the left end of hsync at pin 5 y in to the left end of blanking period at pin 46 blueout with h.blk.r = 000. h.blk.r:000 horizontal blanking right variable range@7 blkr7 y in: horizontal /vertical sync signal pal measure the time t from the left end of hsync at pin 5 y in to the left end of blanking period at pin 46 blueout with h.blk.r = 111. h.blk.r:111 horizontal output stop voltage hstop y in: horizontal /vertical sync signal decrease the current from a sour ce connected to pin 20 and measure the pin 20 voltage at which hout(pin22) stops. h phase bow@16 hbow16 y in: horizontal /vertical sync signal measure the delay time t from the rise of the pin 22 horizontal output pulse to the fall of the y in horizontal sync signal with line 24(ntsc:22) and 167(ntsc:142). caluculat as follow with each value of t is as t1 and t2. hbow16=t2-t1 h phase bow@0 hbow0 y in: horizontal /vertical sync signal measure the delay time t from the rise of the pin 22 horizontal output pulse to the fall of the y in horizontal sync signal with line 24(ntsc:22) and 167(ntsc:142). caluculat as follow with each value of t is as t1 and t2. hbow0=t2-t1 h phase bow: 00000 h phase bow@31 hbow31 y in: horizontal /vertical sync signal measure the delay time t from the rise of the pin 22 horizontal output pulse to the fall of the y in horizontal sync signal with line 24(ntsc:22) and 167(ntsc:142). caluculat as follow with each value of t is as t1 and t2. hbow31=t2-t1 h phase bow: 11111 blue hsync y in t blue hsync y in t 46 5 46 5 20 22 22 5 horizontal out horizontal output 20ire 2.5v t 22 5 22 5 horizontal out horizontal output 20ire 2.5v t horizontal out horizontal output 20ire 2.5v t free datasheet http:///
LV766106C no.a1894-26/40 parameter symbol test point input signal test method bus conditions h phase angle@16 hang16 y in: horizontal /vertical sync signal measure the delay time t from the rise of the pin 22 horizontal output pulse to the fall of the y in horizontal sync signal with line 24(ntsc:22) and 167(ntsc:142).caluculat as follow with each value of t is as t1 and t2. hang16=t2-t1 h phase angle@0 hang0 y in: horizontal /vertical sync signal measure the delay time t from the rise of the pin 22 horizontal output pulse to the fall of the y in horizontal sync signal with line 24(ntsc:22) and 167(ntsc:142).caluculat as follow with each value of t is as t1 and t2. hang0=t2-t1 h phase angle: 00000 h phase angle@31 hang31 y in: horizontal /vertical sync signal measure the delay time t from the rise of the pin 22 horizontal output pulse to the fall of the y in horizontal sync signal with line 24(ntsc:22) and 167(ntsc:142). caluculat as follow with each value of t is as t1 and t2. hang31=t2-t1 h phase angle: 11111 vertical ramp output amplitude @64 vsize64 y in: horizontal /vertical sync signal pal ntsc monitor the pin 17 vertical ramp output and measure the voltage at line 24 (22:ntsc) and line 310 (262:ntsc). calculate as follows:vsize64=vline310(262:ntsc)-vline24(22:ntsc) vertical ramp output amplitude @0 vsize0 y in: horizontal /vertical sync signal pal ntsc monitor the pin 17 vertical ramp output and measure the voltage at line 24 (22:ntsc) and line 310 (262:ntsc). calculate as follows: vsize0=vline310(262:ntsc)-vline24(22:ntsc) vsize: 0000000 vertical ramp output amplitude @127 vsize127 y in: horizontal /vertical sync signal pal ntsc monitor the pin 17 vertical ramp output and measure the voltage at line 24 (22: ntsc) and line 310 (262:ntsc). calculate as follows: vsize127=vline310(262:ntsc)-vline24(22:ntsc) vsize: 1111111 horizontal out horizontal output 20ire 2.5v t horizontal out horizontal output 20ire 2.5v t 22 5 22 5 17 17 17 22 5 horizontal out horizontal output 20ire 2.5v t line 310 line 24 positive vertical ramp output line 310 line 24 positive vertical ramp output line 310 line 24 positive vertical ramp output free datasheet http:///
LV766106C no.a1894-27/40 parameter symbol test point input signal test method bus conditions vertical size correction @0 vsizecomp y in: horizontal /vertical sync signal pal monitor the pin 17 vertical ramp output and measure the voltage at the line 24 and line 310 with vcomp = 000. calculate as follows: va=vline310-vline24 apply 4.0v to pin 15 and meas ure the voltage at the line 24 and line 310 again. calculate as follows: va=vline310-vline24 calculate as follows: vsizecomp=vb/va vcomp:000 fscoreht=1 vertical ramp dc voltage @32 vdc32 y in: horizontal /vertical sync signal pal ntsc monitor the pin 17 vertical ramp output and measure the voltage at line 167(142: ntsc). vertical ramp dc voltage @0 vdc0 y in: horizontal /vertical sync signal pal ntsc monitor the pin 17 vertical ramp output and measure the voltage at line 167(142: ntsc). vdc:000000 vertical ramp dc voltage @63 vdc63 y in: horizontal /vertical sync signal pal ntsc monitor the pin 17 vertical ramp output and measure the voltage at line 167(142: ntsc). vdc:111111 verticalposition @8 vshift8 y in: horizontal /vertical sync signal measure the time t from the beginning of vsync at pin 5 y in to the fall of the pin 17. v.shift:1000 vertical position @0 vshift0 y in: horizontal /vertical sync signal measure the time t from the beginning of vsync at pin 5 y in to the fall of the pin 17. v.shift:0000 vertical position @15 vshift15 y in: horizontal /vertical sync signal measure the time t from the be ginning of vsync at pin 5 y in to the rise of the pin 17. v.shift:1111 line 167 p os iti ve ve rti ca l r a m p ou t put line 167 positive vertical ramp output line 167 p os iti ve ve rti ca l r a m p ou t put 17 17 17 line 310 line 24 positive vertical ramp output 17 t v.out(+):17pin the beginning of vsync 17 5 t v.out(+):17pin the beginning of vsync 17 5 17 5 t v.out(+):17pin the beginning of vsync free datasheet http:///
LV766106C no.a1894-28/40 parameter symbol test point input signal test method bus conditions vertical linearity@16 vlin16 y in: horizontal /vertical sync signal pal monitor the pin 17 vertical ramp output and measure the voltage at line 24, line 167 and 310. assign the respective measured values to va, vb and vc. calculate as follows: vlin16=(vb-va)/(vc-vb) vertical linearity@0 vlin0 y in: horizontal /vertical sync signal pal monitor the p in 17 vertical ramp output and measure the voltage at line 24, line 167 and 310. assign the respective measured values to va, vb and vc. calculate as follows: vlin0=(vb-va)/(vc-vb) vlin:00000 vertical linearity@31 vlin31 y in: horizontal /vertical sync signal pal monitor the pin 17 vertical ramp output and measure the voltage at line 24, line 167 and 310. assign the respective measured values to va, vb and vc. calculate as follows: vlin31=(vb-va)/(vc-vb) vlin:11111 vertical s-shaped correction @16 vscor16 y in: horizontal /vertical sync signal pa l monitor the pin 17 vertical ramp output and measure the voltage at line 26, line 70, line 145, line 189, line 264 and 308. assign the respective measured values to va, vb, vc, vd, ve and vf. calculate as follows: vscor16=0.5((vb-va)+(vf-ve))/ (vd-vc) vertical s-shaped correction @0 vscor0 y in: horizontal /vertical sync signal pal monitor the pin 17 vertical ramp output and measure the voltage at line 26, line 70, line 145, line 189, line 264 and 308. assign the respective measured values to va, vb, vc, vd, ve and vf. calculate as follows: vscor0=0.5((vb-va)+(vf-ve))/ (vd-vc) vsc:10000 vertical s-shaped correction @31 vscor31 y in: horizontal /vertical sync signal pal monitor the pin 17 vertical ramp output and measure the voltage at line 26, line 70, line 145, line 189, line 284 and 308. assign the respective measured values to va, vb, vc, vd, ve and vf. calculate as follows: vscor31=0.5((vb-va)+(vf-ve))/ (vd-vc) vsc:11111 positive vertical ramp output line 167 line 24 line 310 p os iti ve ve rti ca l r a m p ou t put line 167 line 24 line 310 17 17 positive vertical ramp output line 167 line 24 line 310 17 17 17 17 positive vertical ramp output line 145 line 26 line 308 line 189 line 264 line 70 positive vertical ramp output line 145 line 26 line 308 line 70 line 189 line 264 positive vertical ramp output line 145 line 26 line 308 line 70 line 189 line 264 free datasheet http:///
LV766106C no.a1894-29/40 -controller chip (lc873664a) internal 64k-byte rom (rom/cgrom), 640-byte ra m and 352x9-bit crt display ram 8-bit single-chip microcontroller. 1. features flash rom 64k bytes 48 k-byte program rom 16k-byte character generator rom internal ram general-purpose ram: 640 bytes crt display ram: 352 9 bits rom correction ram: 128 bytes minimum bus cycle time 77 ns (13.0 mhz) note: the bus cycle time here refers to the rom read speed. minimum instruction cycle time 231 ns (13.0mhz) osd screen display: 36 characters 8 lines display ram : 352 words (1 word=9 bits) display area: 36 words 8 lines control area: 8 words 8 lines font types: 1632 font, 256 types (including 5 fixed fonts) an arbitrary number of characters can be generated as 1617 or 89 font characters. display colors: 512 colors (analog output) character text, backgrou nd, borders, and full background can be displayed. a maximum 16 colors displayable on a line. display mode specifiable on a line basis. osd mode1, osd mode 2(quarter size), os d mode 3(simplified graphic), caption/text mode vertical display start line and horizontal display start position specifiable on a line basis. shutter function (specifying the disp lay start or stop line) and scroll func tions specifiable on a line basis. horizontal character spacing (9 to 16 dots) (*6) and vertical character spacing (1 to 32 dots) specifiable on a line basis. character size selectable from 10 character sizes on a line basis. (*6) (horizontalvertical) = (11), (12), (22), (24), (1.51), (1.52), (32), (34), (0.50.5), (0.750.5) simplified graphic display (one character (16 16 font) can be painted in 4 or 8 colors.) the half tone control of the tv picture in the background of the character is possible. built-in the oscillation circuit for display (*6)the supported range varies depending on the active di splay mode. refer to the user's guide for details. data slicer function(closed caption format) extracts closed capti on data and xds data. ntsc/pal selectable and line specifiable. ports normal withstand voltage i/o ports ports whose i/o direction can be desi gnated in 1 bit units: 10 (p1n, p3n) ports whose i/o direction can be designated in 4 bit units: 8 (p0n) *if x?tal oscillator is to be used for time-of-day clock, the number of available port 0 is 6. note: threee of the available ports are internal ly connected to the companion signal processin g ic. timers t imer 0: 16-bit tim er/counter with a capture register. timer 1: 16-bit timer/counter th at supports pwm/toggle outputs base timer sio si o0: 8-bit synchronous serial interface sio1: 8-bit asynchronous/synchronous se rial interface (bus mode 1 system) input and output is possible from the te rminal of two systems in bus mode. the two data lines and cloc k lines can be connected. ad converter: 6 bits 5 channels note: one channel is connected internally to the signal processing ic. pwm: 14-bit pwm1 channel free datasheet http:///
LV766106C no.a1894-30/40 digital aft it supports 38mhz , 38.9mhz , 39.5mhz and 45.75mhz as the if frequencies. remote controller receiver circu it (sharing with p03 and int3 pins) noise rejection function (noise f ilter time constant selectable from 1 tcyc,32 tcyc,and 128tcyc) watchdog timer external rc watchdog timer interrupt and reset signals selectable high-speed multiplication/division instructions 16 bits8 bits (execution time: 5 tcyc) 24 bits16 bits (execution time: 12 tcyc) 16 bits8 bits (execution time: 8 tcyc) 24 bits16 bits (ex ecution time: 12 tcyc) interrupts 15 sources, 10 vector addresses 1) provides three levels (low (l), high (h), and highest (x)) of multiplex interrupt control. any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) when interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. for interrupts of the same level, the interrupt into the smallest vector address takes precedence. no. vector address level interrupt source 1 00003h x or l int0 2 0000bh x or l int1 3 00013h h or l int2/t0l 4 0001bh h or l int3/base timer 5 00023h h or l t0h 6 0002bh h or l t1l/t1h 7 00033h h or l sio0 8 0003bh h or l sio1/data slicer 9 00043h h or l vertical sync (vs#)/scan line 10 0004bh h or l port 0 priority levels x > h > l if interrupts of the same level, the one with the smallest vector address takes precedence. subroutine stack levels: 320 levels maxi mum (the stack is allocated in ram.) oscillation circuits rc oscillation circuit (int ernal): for system clock vco oscillation circuit (int ernal): for system clock generation and crt display crystal oscillation circuit: for base timer note:when the base timer count of cloc k accuracy is necessary , use the port terminal (two ports) as the crystal oscillation. (see the [12 -controller chip crystal oscillation circuit and sample characteristics] for details.) standby function halt mode: halts instruction execution while allowing the peripheral circuits to continue operation. 1) oscillation is not halted automatically. 2) there are three ways of resetting halt mode. (1) setting the reset pin to lower level. (2) generation of reset with the watchdog timer. (3) setting at least one of the int0 and int1 pins to the specified level. hold mode: suspends instruction execution a nd the operation of the peripheral circuits. 1) the vco and rc oscillators automatically stop operation. 2) there are four ways of resetting the hold mode. (1) setting the reset pin to the lower level. (2) generation of reset with the watchdog timer. (3) setting at least one of the int0 and int1 pins to the specified level. (4) having an interrupt sour ce established at port 0. rom correction function executes the correction program on detection of a match with the program counter value. correction program area size: 1 28 bytes (4 vector addresses) development tools emulater: tcb87 (type b or typ c) (onchip debugger interface board) + ecb873600a ( evaluation chip board + lc873600eva) + pod36-jct (connecter between ev aluation chip board and pod) + pod76600 (pod + lv766xxeva) free datasheet http:///
LV766106C no.a1894-31/40 2. -controller chip system block diagram interrupt control standby control ir pla clock generator vco rc bus interface port 0 port 1 sio0 sio1 timer 0 timer 1 port 3 alu flash rom pc acc b register c register psw rar ram stack pointer watchdog timer pwm int0-int3 noise filter base timer adc rom correct pll data slicer xtal reference clock osd contro l circuit cgrom control vram dds d-aft free datasheet http:///
LV766106C no.a1894-32/40 3. -controller chip pin function chart pin name i/o description option cpugnd - - power supply pin no cpuvdd - power supply pin no cpuvdd2 - power supply pin no port 0 ? 8-bit i/o port ? i/o specifiable in 4 bit units ? pull-up resistors can be turned on and off in 4 bit units. ? hold reset input ? port 0 interrupt input ? pin functions p00: int0 input/hold reset input/timer 0l capture input/watchdog timer output/ sio0 data output p01: int1 input/hold reset input/timer 0h capture input/sio0 data input/bus i/o p02: sio0 clock i/o p03: int3 input (with noise filter input)/timer 0 event input/ timer 0h capture input p04: ad conversion input terminal (an4) p05: ad conversion input terminal (an5) p06: ad conversion input terminal (an6)/output terminal for 32.768khz crystal oscillation (xt2) p07: ad conversion input terminal (an7)/input terminal for 32.768khz crystal oscillation (xt1) interrupt acknowledge type rising falling rising & falling h level l level int0 int1 int3 p00 to p07 i/o the two terminal of p00, p01, p04 and p05 can be used as led driver. p00-p03: no p04-p07: ye s port 1 p11 to p17 i/o ? 7-bit i/o port ? i/o specifiable in 1 bit units ? pull-up resistors can be turned on and off in 1 bit units. ? pin functions p13: tvpwmd output p14: sio1 data input/bus i/o p15: sio1 clock i/o p16: sio1 data input / bus i/o / data output p17: sio1 clock i/o /t1pwml output ye s port 3 ? 3-bit i/o port (internal connected terminal) ? i/o specifiable in 1 bit units ? pin functions p30,p31: internal communication interface terminal: p32 : int2 input / timer 0 event input/ timer 0l capture input interrupt acknowledge type rising falling rising & falling h level l level int2 p30 to p32 i/o no res# input reset pin no filt output internal pll filter pin for system clock no vddi1 - power supply pin (internal connected terminal) no vddi2 - power supply pin (internal connected terminal) no resi# input reset pin (internal connected terminal) no xtin input reference clock input (internal connected terminal) no cvin input video input pin (internal connected terminal) no peout output pedestal level output (internal connected terminal) no vs# input vertical sync input pin (internal connected terminal) no hs# input horizontal sync input pin (internal connected terminal) no r output red (r) rgb video output pin (internal connected terminal) no g output green (g) rgb video output pin (internal connected terminal) no b output blue (b) rgb video output pin (internal connected terminal) no bl1 output fast blanking 1 control output pin (internal connected terminal) no bl2 output fast blanking 2 control output pin (internal connected terminal) no ddsout output dds color sub-carrier output pin (internal connected terminal) no ddsys input dds color system selection pin (internal connected terminal) no ddsin input dds clock input pin (internal connected terminal) no daftin input if carrier input pin (internal connected terminal) no free datasheet http:///
LV766106C no.a1894-33/40 4. -controller chip port output types the table below lists the types of port outputs an d the presence/absence of a pull-up resistor. data can be read into any input port even if it is in the output mode. port name option selected in units of option type output type pull-up resistor p00 to p03 - no nch-open drain no 1 cmos programmable (*8) p04 to p07 1 bit 2 nch-open drain no 1 cmos programmable p11 to p17 1 bit 2 nch-open drain programmable p30 to p31 - no nch-open drain yes p32 - no nch-open drain no (*8) programmable pull-up resistors for port 0 are controlled in 4 bit units (p04 to p07). *connect the ic as s hown below to minimize th e noise input to the cpuv dd pin. 5. -controller chip electrical characteristics ta=-10deg to +65deg, v ss =0v limits parameter symbol pins conditions v dd [v] min typ max unit iih(1) ports0,1 ? output disable ? pull-up mos tr.off ? v in =v dd (including the off-leak current of the output tr.) 4.5 to 5.5 1 high level input current iih(2) res# v in =v dd 4.5 to 5.5 1 iil(1) ports0,1 ? output disable ? pull-up mos tr.off ? v in =v ss (including the off-leak current of the output tr.) 4.5 to 5.5 -1 low level input current iil(2) res# v in =v ss 4.5 to 5.5 -1 a high level output voltage v o h ports04-07, ports1 i o h=-1.0ma 4.5 to 5.5 v dd -1 i o l=10ma 4.5 to 5.5 1.5 v o l(1) ports02,03 ports06,07 ports1 i o l=1.6ma 4.5 to 5.5 0.4 low level output voltage v o l(2) ports00,01, ports04,05 i o l=8.0ma 4.5 to 5.5 0.4 v pull-up mos tr. resistan ce rpu ports04-07,1 v o h=0.9v dd 4.5 to 5.5 15 40 70 k ? bus terminal short circuit resistance for internal communication rbs ? p14-p30 ? p15-p31 ? p14-p16 ? p15-p17 4.5 to 5.5 130 300 ? hysteresis voltage vhis ports0 0-03,1 ? res# 4.5to 5.5 0.35 v . power supply lsi cpuv dd cpugnd cpuv dd 2 1 f free datasheet http:///
LV766106C no.a1894-34/40 6. -controller chip sio0 characteristics(*9) ta=-10deg to +65deg, v ss =0v limits parameter symbol pins conditions v dd [v] min typ max unit cycle tsck(1) 2 low level pulse-width tsckl(1) 1 tsckh(1) see the figure 4. 1 input clock high level pulse-width tsckha(1a) sck0(p02) ? continuous data transmitting and receiving mode ? see the figure 4. (*10) 4.5 to 5.5 4 cycle tsck(2) 4/3 tcyc low level pulse-width tsckl(2) 1/2 tsckh(2) ? at the cmos output s election ? see the figure 4. 1/2 tsck serial clock output clock low level pulse-width tsckha(2a) sck0(p02) ? at the cmos output ? continuous data transmitting and receiving mode ? see the figure 4. 4.5 to 5.5 tsckh(2) + 2tcyc tsckh(2)+ (10/3)tcyc tcyc data setup time tsdi(1) 0.03 serial input data hold time thdi(1) si0(p01) sb0(p01) ? define for rising of siocl k . ? see the figure 4. 4.5 to 5.5 0.03 tddo(1) ? continuous data transmitting and receiving mode (*11) (1/3)tcyc +0.05 input clock tddo(2) ? synchronous 8-bit mode (*11) 1tcyc +0.05 serial outpu output clock output delay time tddo(3) so0(p00) sb0(p01) (*11 4.5 to 5.5 (1/3)tcyc +0.05 s (*9) this limited value is theoretical figure. be sure to ensure the margin in accordance with use situation. (*10) when using the serial clock input with cont inuous data transmitting and receiving mode, lengthen time from the set of the cereal clock of si0run in the state of "h" to the falling of the first cereal clock when it begins to send and receiv e continuous data more than tsckha. (*11) this is defined for falling of sioc lk and it is defined as time until output change start in open drain output. (see the figure 4) 7. -controller chip sio1 characteristi cs (*11) / ta=-10deg to +65deg, v ss =0v limits parameter symbol pins conditions v dd [v] min typ max unit cycle tsck(3) 2 low level pulse-width tsckl(3) 1 input clock high level pulse-width tsckh(3) sck1(p15) see the figure 4. 4.5 to 5.5 1 cycle tsck(4) 2 tcyc low level pulse-width tsckl(4) 1/2 serial clock output clock high level pulse-width tsckh(4) sck1(p15) ? at the cmos output selection ? see the figure 4. 4.5 to 5.5 1/2 tsck data setup time tsdi(2) 0.03 serial input data hold time thdi(2) si1(p14) sb1(p14) ? define for rising of sioclk. ? see the figure 4. 4.5 to 5.5 0.03 serial output output delay time tddo(4) so1(p16) sb1(p14) ? define for falling of sioclk. ? define as time until output change start in open drain output. ? see the figure 4. 4.5 to 5.5 (1/3)tcyc +0.05 s (*12) this limited value is theoretical figure. be sure to ensure the margin in accordance w ith use situation. free datasheet http:///
LV766106C no.a1894-35/40 8. -controller chip pulse input conditions / ta=-10deg to +65deg, v ss =0v limits parameter symbol pins conditions v dd [v] min typ max unit tpih(1) tpil(1) int0,int1,int2 ? interrupt acceptable ? timer0, 1 event input enabled 4.5 to 5.5 1 tpih(2) tpil(2) int3/p03 (1/1 is selected for noise rejection clock.) ? interrupt acceptable ? timer0, 1 event input enabled 4.5 to 5.5 2 tpih(3) tpil(3) int3/p03 (1/32 is selected for noise rejection clock.) ? interrupt acceptable ? timer0, 1 event input enabled 4.5 to 5.5 64 tpih(4) tpil(4) int3/p03 (1/128 is selected for noise rejection clock.) ? interrupt acceptable ? timer0, 1 event input enabled 4.5 to 5.5 256 tcyc high/low level pulse width tpil(5) res# reset acceptable 4.5 to 5.5 200 s 9. -controller chip ad converter charact eristics / ta=-10deg to +65deg, v ss =0v limits parameter symbol pins conditions v dd [v] min typ max unit resolution n 6 bit absolute precision et (*13) 1 lsb conversion time tcad until result of conversion is ensured after vref selection 1 bit conversion time = 3 tcyc 0.636 s analog input voltage range vain v ss v dd v iainh vain=v dd 1 analog port input current iainl an3, an4~an7 (p04-p07) va i n = v ss 4.5 to 5.5 -1 a (*13) absolute precision does not in clude quantizing error (1/2lsb). free datasheet http:///
LV766106C no.a1894-36/40 10. -controller chip sample current dissipation characteristics / ta=-10deg to +65deg, v ss =0v the sample current dissipation characteristics is the meas urement result of sanyo provided evaluation board when the recommended circuit parameters shown in the sample oscillation circuit characteristics are used externally. the currents through the output transistors and the pull-up mos transistors are ignored limits parameter symbol pins conditions v dd [v] min typ max unit iddop(1) cpuv dd reference clock=4.43mhz crystal oscillation operating mode: bipchip system clock: v co (13.0mhz) vco for osd operating built-in rc oscillation stops at the 1/1 frequency dividing osd, dsl enabled 4.5 to 5.5 31 42 ma current dissipation during basic operation (*14) (*15) iddop(2) cpuv dd reference clock=4.43mhz crystal oscillation stanby mode: bipchip system clock: reference clock frequency dividing (32khz) v co for the main clock and for osd stops built-in rc oscillation stops at the 1/2 frequency dividing 4.5 to 5.5 2 2.7 ma iddhalt(1) cpuv dd halt mode reference clock=4.43mhz crystal oscillation stanby mode: bipchip system clock: vco (13.0mhz) vco for osd stops built-in rc oscillation stops osd, dsl enabled 4.5 to 5.5 5 8 ma iddhalt(2) cpuv dd halt mode reference clock=4.43mhz crystal oscillation stanby mode: bipchip system clock: built-in rc oscillation v co for the main clock and for osd stops at the 1/1 frequency dividing 4.5 to 5.5 1.7 3.2 ma current dissipation in halt mode (*14) (*15) iddhalt(3) cpuv dd halt mode reference clock=4.43mhz crystal oscillation stanby mode: bipchip system clock: reference clock frequency dividing (32khz) v co for the main clock and for osd stops built-in rc oscillation stops at the 1/2 frequency dividing 4.5 to 5.5 1.3 2 ma current dissipation in hold mode (*15) iddhold cpuv dd hold mode all oscillation stop reference clock=4.43mhz crystal oscillation stanby mode:bipchip 4.5 to 5.5 1.2 1.9 ma (*14) the currents of the output transistors and the internal pull-up mos transistors are ignored. (*15) 4.43mhz crystal oscillatio n current is contained. free datasheet http:///
LV766106C no.a1894-37/40 11. -controller chip crystal oscillation circuit and sample characteristics ta=-10deg to +65deg, v ss =0v when the base timer count of clock accuracy is necessary , lc873664a can use the port terminal (p06,p07) as the crystal oscillation (see the figure 1). the sample oscillation circuit characteristics and recommended oscillation circuit when port terminal (p06, p07) is us ed as xtal oscillation terminal are shown below. the sample oscillation circuit char acteristics in the tabl e below is based on the following conditions: ? recommended circuit parameters are verified by an oscillato r manufacturer using a sanyo provided oscillation evaluation board. ? sample characteristics are the result of the evaluation with the recommended circuit parameters connected externally. recommended circuit parameters tmsxtal (*16) oscillation stabilizing time frequency manufacturer oscillator c1 c2 rf rd operating supply voltage range typ max notes 32.768khz epson toyocom mc-306 18pf 18pf open 390k ? 4.5 to 5.5v 1.0s 1.5s applicable cl value = 12.5pf smd-type (*16) the oscillation stab ilization time refers to the time interval that is required for th e oscillation to get stabilized aft er the instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the oscillation to get stabilized after the hold mode is reset (see the figure 3). the sample oscillation circuit characteristics may differ applicat ions. for further assistance, please contact with oscillator manufacturer with the following notes in your mind. ? since the oscillation frequency precision is affected by wiring capacity of the application board, etc., adjust the oscillation frequency on the production board. ? the above oscillation frequency and th e operating supply voltage range are based on the operating temperature of -10deg to +65deg. for the use with the temperatur e outside of the range herein , or in the applications requiring high reliability such as car produc ts, please consult with oscillator manufacturer ? when using the oscillator which is not shown in th e sample oscillation circuit characteristics, please consult with sanyo sales personnel. since the oscillation circuit characteristics are affected by the noise or wiring capacity because the circuit is designed with low gain in order to redu ce the power dissipation, refer to the following notices. ? the distance between the clock i/o terminal (p07/xt1 terminal p06/xt2 terminal) and external parts should be as short as possible. ? the capacitors? vss should be allocate d close to the microcontroller?s cpugnd terminal and be away from other gnd. ? the signal lines with rapid stat e changes or with large current should be allocated away from the oscillation circuit. figure 1 recommended oscillation circuit. figure 2 the point of ac timing measure. rd c1 c2 x?tal xt2 (p06) xt1 (p07) rf 0.5v dd free datasheet http:///
LV766106C no.a1894-38/40 figure 3 oscillation stable time. power supply res# built-in rc oscillation v co 1 xt1,xt2 reset time tmsvco tmsxtal indifinite reset instruction execution reset time and oscillation stable time built-in rc oscillation v co 1 xt1,xt2 status invalid the hold release si g nal valid the hold release si g nal tmsvco tmsxtal hold halt cpuv dd 0v hold release signal and os cillation stable time tpil ( 5 ) xtal oscillation enable signal ( enable state ) xtal oscillation enable signal free datasheet http:///
LV766106C no.a1894-39/40 figure 4 serial i/o wave. tpil tpih figure 5 pulse input timing wave. - filt + 1m 100 33000pf 2.2f figure 6 filt recommended circuit. (note) place filt parts on board as cl ose to the microcontroller as possible. data ram transmission time ( sio0 onl y) d ata ram transmission time () di0 di7 di2 di3 di4 di5 di6 di8 do0 do7 do2 do3 do4 do5 do6 do8 di1 do1 sioclk: datain: dataout: dataout: datain: sioclk: dataout: datain: sioclk: tsc k tsckl tsckh thdi tsdi tddo tsckl tsckha thdi tsdi tddo free datasheet http:///
LV766106C ps no.a1894-40/40 sanyo semiconductor co.,ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rate d values (such as maximum ra tings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qual ity high-reliability products, however, any and all semiconductor products fail or malfunction with some probabi lity. it is possible that these probabilistic failures or malfunction could give rise to acci dents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or e vents cannot occur. such measures include but are not limited to protective circuits and error prevention c ircuits for safe design, redundant design, and structural design. upon using the technical information or products descri bed herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable f or any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. information (including circuit diagr ams and circuit parameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equi pment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor c o.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities conc erned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any in formation storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. - + 1f cpuvdd2 figure 7 cpuv dd 2 recommended circuit. (note) place cpuv dd 2 parts on board as close to th e microcontroller as possible. * refer to the user?s manual of lc873600 series,when you know the details about -controller. this catalog provides information as of december, 2010. specifications and inform ation herein are subject to change without notice. free datasheet http:///

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